1. Field of the Invention
This application is related to integrated circuits and more particularly to data communications links between integrated circuits.
2. Description of the Related Art
To properly recover data received by an integrated circuit node and transmitted across a data communications link by another integrated circuit node, the receiving node must sample the data during an appropriate phase of the data signal. A transmitting node compliant with an exemplary communications link may transmit, on a separate signal line, a reference clock signal for use in sampling commands, addresses or data (hereinafter, “data”) by the receiving node. However, introduction of skew between a received data signal and a received sample clock signal (e.g., skew introduced by the channel of the communications link, the receiver, or other sources) may compromise data recovery. For example, if skew between the reference clock signal and the received data signal causes data transitions to approach the sampling point, the data transitions may fall within the clock signal setup time of a sampling device (e.g., flip-flop or other state element) causing errors in data recovery. In addition, the phase relationship between the received clock signal and the received data signal may not be stationary, which adds complexity to clock and data recovery operations.